1. Field of the Invention
The present invention relates to a method for making a semiconductor device including a MOS transistor or a MOS capacitor.
2. Prior Art
In a manufacturing process of semiconductor devices such as a MOS transistor or a MOS capacitor, impurity ions are doped into the surface of a semiconductor substrate after a conductive layer is formed on the semiconductor substrate via an insulating layer. The impurity ions are doped in order to form a source/drain region or an LDD (Lightly Doped Drain-source) region, or to provide conductivity to the conductive layer.
A conventional method of making the aforementioned devices is explained with reference to the figures. FIGS. 20A-20D are cross-sectional views showing conventional process steps for making a MOS transistor. The MOS transistor comprises gate insulating film 74, gate electrode 75, side-wall 76 formed on a p-type silicon substrate 70 having p-well region 71.
First, a polycrystalline silicon film is patterned to form gate electrode 75 on a p-type silicon substrate 70 having p-well region 71, LDD region 72 and source/drain region 73 (FIG. 20A).
Next, Arsenic (As) ions are doped as a first implantation with the acceleration energy of 30 KeV at the dosage of 3.times.10.sup.13 atoms/cm.sup.2 to form LDD region 72 (FIG. 20B). Then, sidewall 76 is formed by way of etching back a 100 nm-thick High Temperature Oxide (HTO) layer (FIG. 20C). Further, a second ion implantation of As ions is carried out with an acceleration energy of 30 KeV at the dosage of 3.times.10.sup.15 atoms/cm.sup.2 to form source/drain region 73 (FIG. 20D). In this step, LDD region 72 will not merge with source/drain region 73 since the LDD region 72 is shielded by the sidewall 76 from the second ion implantation.
By the aforementioned process, a semiconductor device (MOS transistor) having an LDD region is completed. The LDD region 72 is formed for the purpose of preventing the generation of hot carriers and for the purpose of preventing the extension of the source/drain region to reach below the gate electrode 75.
In the conventional process, formation of a damaged layer in the gate insulating layer 74 due to the ion implantation degrades the device performance, which becomes more and more serious as the dimension of the device gets smaller and required performance gets higher.
The mechanism therefore is given below.
The gate insulating layer 74 suffers from not only degradation but, in extreme cases, breakdown. It is believed that the degradation is due to the silicon-oxygen bond slashed by incident implant ions or holes/electrons trapped in states formed in the gate insulating layer 74.
This sort of degradation is also observed in a capacitor (MOS capacitor) formed on a semiconductor substrate. A typical capacitor on a semiconductor substrate includes a well region in the semiconductor substrate as the lower capacitor electrode, an insulating film on the lower electrode as the capacitor insulating layer and an upper capacitor electrode on the capacitor insulating film. In a capacitor device of this structure, the upper electrode is typically formed with heavily doped polycrystalline silicon.
The polycrystalline silicon must be doped with a density higher than 10.sup.14 atoms/cm.sup.2. The high density doping can form a damaged layer in the capacitor insulating layer as is the case of a MOS transistor gate insulating layer.
It is pointed out that the formation of the damaged layer depends not only on the dosage but the thickness of the insulating layer. Recently, an insulating layer with the thickness as thin as 5 nm or less is in the scope of mass production. A thin insulating layer of this range is naturally vulnerable to ion implantation impact and could be damaged by implantation of relatively small dosages, such as 10.sup.14 atoms/cm.sup.2 or less.
Hence, the prime object of the present invention is to increase the reliability of a semiconductor device by providing a damage free insulating layer.